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1 for more information www.linear.com/ltm4632 typical application features description ultrathin, triple output, step-down module regulator for ddr-qdr4 memory the lt m ? 4632 is an ultrathin triple output step-down module ? (power module) regulator to provide complete power solution for ddr-qdr4 sram. operating from a 3.6v to 15v input voltage, the ltm4632 supports two 3a output rails, both sink and source capable, for vddq and vtt, plus a 10ma low noise reference vttr output. both vtt and vttr track and are equal to vddq/2. housed in a 6.25mm 6.25mm 1.82mm lga and 6.25mm 6.25mm 2.42mm bga packages, the ltm4632 includes the switching controller, power fets, inductors and sup - port components. alternatively, the power module can also be configured as a two phase single 6a output vtt. only a few ceramic input and output capacitors are needed to complete the design. the ltm4632 supports selectable burst mode operation (ch1 only) and output voltage tracking for supply rail sequencing. its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability. fault protection features include overvoltage input, over- current and overtemperature protection. the ltm4632 is available with snpb (bga) or rohs com - pliant terminal finish qdr4 memory power module regulator output efficiency vs load current n complete ddr-qdr4 sram power solution including vddq, vtt, vttr (or vref) n solution in 0.5cm 2 (dual-sided pcb) n wide input voltage range : 3.6v to 15v n 3.3v input compatible with v in tied to intv cc n 0.6v to 2.5v output voltage range n dual 3a dc output current with sink and source capability n 1.5%, 10ma buffered vttr = vddq/2 output n 3a vddq + 3a vtt or dual phase single 6a vtt n 1.5% maximum total output voltage regulation error over load, line and temperature n current mode control, fast transient response n external frequency synchronization n multiphase parallelable with current sharing n selectable burst mode ? operation n overvoltage input and overtemperature protection n power good indicator n ultrathin 6.25mm 6.25mm 1.82mm lga and 6.25mm 6.25mm 2.42mm bga packages l , lt, ltc, ltm, module, burst mode, linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. 52.3k vddq 4632 ta01a 10f 25v v in 3.6v to 15v vddq 1.3v, 3a 22f 4v 22f 4v v out1 vtt 0.65v, 3a vttr 0.65v, 10ma v out2 comp1 vttr fb1 gnd ltm4632 pgood1 pgood2 v in run1 run2 intv cc sync/mode track/ss1 v ddqin comp2 load current (a) 0 65 efficiency (%) 90 80 75 70 85 95 2 3 1 4632 ta01b 12v input 5v input applications n ddr memory power supply n general purpose point-of-load conversion n telecom, networking and industrial equipment lt m4632 4632fc
2 for more information www.linear.com/ltm4632 pin configuration absolute maximum ratings v in ............................................................. C 0.3v to 16v v out ............................................................. C 0.3v to 6v pgoo d1 , pgoo d2 ..................................... C 0.3v to 16v ru n1 , ru n2 ...................................... C 0.3v to v in + 0.3v intv cc , track/s s1 , v ddqin , vttr ......... C 0.3v to 3.6v mode/sync, com p1 , com p2 , fb1 , fb2 ................................................ C 0.3v to intv cc operating internal temperature range (notes 2, 3, 5) ........................................ C 40 c to 125 c storage temperature range .................. C 55 c to 125 c peak solder reflow body temperature ................. 260 c (note 1) lga package 25-lead (6.25mm 6.25mm 1.82mm) bga package 25-lead (6.25mm 6.25mm 2.42mm) top view comp2 sync/ mode gnd v out1 fb1 pgood1 track/ss1 a 5 1 2 3 4 pgood2 v ddqin vttr intv cc run2 b c d e comp1 gnd gnd run1 gnd v in v in v in v in v out2 t jmax = 125c, t jctop = 17c /w, t jcbottom = 11c / w, t jb +t ba = 22c /w, t ja = 20c/w weight = 0.21g (see pin functions, pin configuration table) part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4632ev#pbf au (rohs) ltm4632v e4 lga 3 C40c to 125c ltm4632iv#pbf au (rohs) ltm4632v e4 lga 3 C40c to 125c ltm4632ey#pbf sac305 (rohs) ltm4632y e1 bga 3 C40c to 125c ltm4632iy#pbf sac305 (rohs) ltm4632y e1 bga 3 C40c to 125c ltm4632iy snpb (63/37) ltm4632y e0 bga 3 C40c to 125c ? consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking : www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and tray drawings : www.linear.com/packaging order information http: //www.linear.com/product/ltm4632#orderinfo lt m4632 4632fc
3 for more information www.linear.com/ltm4632 electrical characteristics symbol parameter conditions min typ max units v in input dc voltage l 3.6 15 v v in_3.3 3.3v input dc voltage v in = intv cc l 3.1 3.3 3.5 v v out1(range) v out2(range) output voltage range v in = 3.6v to 15v l l 0.6 2.5 1.8 v v output specification (channel 1) v out1 (dc) ch1 output voltage, total variation with line and load c in = 22f, c out = 100f ceramic r fb1 = 51.7k, mode = gnd, i out = C3a to 3a l 1.28 1.30 1.32 v i out1 (dc) ch1 output continuous current range v in = 12v, v out1 = 1.3v (note 3) C3 3 a iq1(v in ) ch1 input supply bias current v in = 12v, v out1 = 1.3v, mode = gnd v in = 12v, v out1 = 1.3v, mode = intv cc shutdown, run1 = gnd 13 400 40 ma a a is1(v in ) ch1 input supply current v in = 12v, v out1 = 1.3v, i out = 3a 0.4 a v out1 (line)/v out1 ch1 line regulation accuracy v out1 = 1.3v, v in = 3.6v to 15v, i out1 = 0a l 0.01 0.05 %/v v out1 (load)/v out1 ch1 load regulation accuracy v out1 = 1.3v, i out = C3a to 3a l 0.2 1.0 % v out1 (ac) ch1 output ripple voltage i out = 0a, c out = 47f ceramic v in = 12v, v out1 = 1.3v 30 mv v out1 (start) ch1 turn-on overshoot i out = 0a, c out = 47f ceramic, track/ss1 = C0.1f, v in = 12v, v out1 = 1.3v 30 mv t start turn-on time c out = 100f ceramic, track/ss1 = 0.01f no load, v in = 12v, v out1 = 1.3v 1.2 ms v outls1 ch1 peak deviation for dynamic load load: 0% to 25% to 0% of full load c out = 47f ceramic, v in = 12v, v out1 = 1.3v 85 mv t sett le1 ch1 settling time for dynamic load step load: 0% to 25% to 0% of full load c out = 47f ceramic, v in = 12v, v out1 = 1.3v 20 s ioutpk1 ch1 output current limit v in = 12v, v out1 = 1.3v 4.5 a output specification (channel 2) v out2 (dc) ch2 output voltage, total variation with line and load c in = 22f, c out = 100f ceramic v ddqin = 1.3v, mode = gnd, i out = C3a to 3a l 637 650 663 mv i out2 (dc) ch2 output continuous current range v in = 12v, v ddqin = 1.3v (note 3) C3 3 a iq2(v in ) ch2 input supply bias current v in = 12v, v ddqin = 1.3v, mode = gnd shutdown, run2 = 0 7 40 ma a is2(v in ) ch2 input supply current v in = 12v, v ddqin = 1.3v, i out = 3a 0.25 a v out2 (line)/v out2 ch2 line regulation accuracy v ddqin = 1.3v, v in = 3.6v to 15v, i out2 = 0a l 0.01 0.05 %/v v out2 (load)/v out2 ch2 load regulation accuracy v ddqin = 1.3v, i out = C3a to 3a l 0.2 1.0 % v out2 (ac) ch2 output ripple voltage i out = 0a, c out = 100f ceramic v in = 12v, v ddqin = 1.3v 30 mv v outls2 ch2 peak deviation for dynamic load load: 0% to 25% to 0% of full load c out = 47f ceramic, v in = 12v, v out1 = 1.3v 85 mv t settle2 ch2 settling time for dynamic load step load: 0% to 25% to 0% of full load c out = 47f ceramic, v in = 12v, v out1 = 1.3v 20 s ioutpk2 ch2 output current limit 4.5 a the l denotes the specifications that apply over the specified internal operating temperature range (note 2). specified as each individual output channel at t a = 25c (note 2), v in = 12v , unless otherwise noted, per the typical application in figure 19 lt m4632 4632fc
4 for more information www.linear.com/ltm4632 note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the ltm4632 is tested under pulsed load conditions such that t j t a . the ltm4632 e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4632i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. electrical characteristics the l denotes the specifications that apply over the specified internal operating temperature range (note 2). specified as each individual output channel at t a = 25c (note 2), v in = 12v , unless otherwise noted, per the typical application in figure 19 symbol parameter conditions min typ max units control section v fb1 voltage at v fb1 pin i out = 0a, v out1 = 1.3v l 0.593 0.600 0.607 v i fb1 current at v fb1 pin (note 4) 30 na rfbhi1 resistor between v out1 and v fb1 pins 60.00 60.40 60.80 k vttr vttr voltage reference v ddqin = 1.3v, ivttr = 10ma, cvttr < 10nf l 0.492x v ddqin 0.50x v ddqin 0.508x v ddqin v v run1 , v run2 run pin on threshold run threshold rising run threshold falling 1.18 0.95 1.28 1.01 1.39 1.05 v v i run1 , i run2 run pin leakage current 0 1 a i track/ss1 track/ss1 pin soft-start pull-up current track/ss1 = 0v 1.2 a t on(min) minimum on-time (note 4) 20 ns t off(min) minimum off-time (note 4) 45 ns vpgood pgood trip level v fb with respect to 0.6v v out2 with respect to v ddqin /2 (note 4) ramping negative ramping positive C8 8 C14 14 % % rpgood pgood pull-down resistance 1ma load 15 v intvcc internal v cc voltage v in = 3.6v to 15v 3.1 3.3 3.5 v v intvcc load reg intv cc load regulation i cc = 0 to 50ma 1.3 % f osc oscillator frequency 1 mhz sync sync threshold voltage 0.95 v i sync/mode mode input current sync/mode = intv cc C1.5 a note 3. see output current derating curves for different v in , v out and t a . note 4. 100% tested at wafer level. note 5. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. lt m4632 4632fc
5 for more information www.linear.com/ltm4632 typical performance characteristics 1v output transient response 1.2v output transient response 1.5v output transient response 1.8v output transient response 2.5v output transient response start-up with no load current applied efficiency vs load current at 3.6v in efficiency vs load current at 5v in efficiency vs load current at 12v in load current (a) 0 efficiency (%) 100 95 85 90 80 70 75 65 60 1.0 0.5 2.0 4632 g01 3.0 1.5 2.5 1v out 1.2v out 1.5v out 1.8v out 2.5v out load current (a) 0 efficiency (%) 100 95 85 90 80 70 75 65 60 1.0 0.5 2.0 4632 g02 3.0 1.5 2.5 1v out 1.2v out 1.5v out 1.8v out 2.5v out load current (a) 0 efficiency (%) 100 95 85 90 80 70 75 65 60 1.0 0.5 2.0 4632 g03 3.0 1.5 2.5 1v out 1.2v out 1.5v out 1.8v out 2.5v out v in = 12v v out = 1v f s = 1mhz output capacitor = 1 47f ceramic load step = 2.25a to 3a load step 1a/div v out ac-coupled 50mv/div 4632 g04 20s/div v in = 12v v out = 1.8v f s = 1mhz output capacitor = 1 47f ceramic load step = 2.25a to 3a load step 1a/div v out ac-coupled 50mv/div 4632 g07 20s/div v in = 12v v out = 1.2v f s = 1mhz output capacitor = 1 47f ceramic load step = 2.25a to 3a load step 1a/div v out ac-coupled 50mv/div 4632 g05 20s/div v in = 12v v out = 2.5v f s = 1mhz output capacitor = 1 47f ceramic load step = 2.25a to 3a load step 1a/div v out ac-coupled 50mv/div 4632 g08 20s/div v in = 12v v out = 1.5v f s = 1mhz output capacitor = 1 47f ceramic load step = 2.25a to 3a load step 1a/div v out ac-coupled 50mv/div 4632 g06 20s/div v in = 12v v out = 1.8v f s = 1mhz i out = 0a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic soft-start capacitor = 0.1f v out 1a/div i in 0.5a/div sw 10v/div 4632 g09 20s/div lt m4632 4632fc
6 for more information www.linear.com/ltm4632 v in = 12v v out = 1.8v f s = 1mhz i out = 3a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic soft-start capacitor = 0.1f v out 1v/div i in 0.5a/div sw 10v/div 4632 g10 20ms/div v in = 12v v out = 1.8v f s = 1mhz i out = 0a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic v out 1v/div i in 2a/div sw 10v/div 4632 g13 20s/div v in = 12v v out = 1.8v f s = 1mhz i out = 0a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic v out 1v/div i in 2a/div sw 10v/div 4632 g11 20s/div v in = 12v v out = 1.8v f s = 1mhz i out = 0a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic v out ac-coupled 50mv/div sw 5v/div 4632 g14 1s/div v in = 12v v out = 1.8v f s = 1mhz i out = 3a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic v out 1v/div i in 2a/div sw 10v/div 4632 g12 20s/div v in = 12v v out = 1.8v f s = 1mhz i out = 0a input capacitor = 1 22f ceramic output capacitor = 1 47f ceramic v out 1v/div run 10v/div sw 5v/div 4632 g15 50ms/div typical performance characteristics recover from short-circuit with no load current applied steady-state output voltage ripple start-up into pre-biased output start-up with 3a load current applied short-circuit with no load current applied short-circuit with 3a load current applied lt m4632 4632fc
7 for more information www.linear.com/ltm4632 pin functions v in ( a2, b3, d3, e2) : power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. v out1 (d1, e1), v out2 (a1, b1): power output pins of each switching mode regulator. apply output load be- tween these pins and gnd pins. recommend placing out - put decoupling capacitance directly between these pins and gnd pins. gnd (c1-c2, c4, b5, d5): power ground pins for both input and output returns. pgood1 ( d4) : output power good with open-drain logic of the channel 1 switching mode regulator. pgoo d1 is pulled to ground when the voltage on the fb1 pin is not within 8% (typical) of the internal 0.6v reference. this threshold has 15mv of hysteresis. pgood2 ( b4) : output power good with open-drain logic of the channel 2 switching mode regulator. pgoo d2 is pulled to ground when the voltage on the v out2 pin is not within 8% (typical) of the v ddqin /2 voltage. this threshold has 15mv of hysteresis. sync/mode (c5) : mode select and external synchronization input. tie this pin to ground to force continuous synchronous operation at all output loads. floating this pin or tying it to intv cc enables high effi - ciency burst mode operation at light loads. drive this pin with a clock to synchronize the ltm4632 switching frequency. an internal phase-locked loop will force the bottom power nmoss turn on signal to be synchronized with the rising edge of the clock signal. when this pin is driven with a clock, forced continuous mode is automati - cally selected. intv cc ( c3) : internal 3.3v regulator output of the switching mode regulator channel. the internal power drivers and control circuits are powered from this volt - age. this pin is internally decoupled to gnd with a 2.2f low esr ceramic capacitor. no more external decoupling capacitor needed. run1 ( d2), run2 ( b2) : run control input of each switching mode regulator channel. enables chip opera - tion by tying run above 1.28v . tying this pin below 1v shuts down the specific regulator channel. do not float this pin. comp1 ( e5), comp2 ( a5) : current control threshold and error amplifier compensation point of each switching mode regulator channel. the current comparators trip threshold is linearly proportional to this voltage, whose normal range is from 0.3v to 1.8v. the device is inter - nal compensated. tie comp pins together in dual phase single output vtt configuration. see the applications information section for details. fb1 ( e4) : the negative input of the error amplifier for the channel 1 switching mode regulator. internally, this pin is connected to v out1 with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between fb1 and gnd pins. connect this pin to intv cc in dual phase single output vtt configuration. see the applications information sec - tion for details. track/ss1 (e3): output tracking and soft-start pin of the channel 1 switching mode regulator. it allows the user to control the rise time of the output voltage. putting a voltage below 0.6v on this pin bypasses the internal reference input to the error amplifier, instead it servos the fb pin to the track/ss voltage. above 0.6v , the tracking function stops and the internal reference resumes control of the error amplifier. there s an internal 1.2a pull-up current from intv cc on this pin, so putting a capacitor here provides a soft-start function. vttr ( a3): reference output. this output is used to sup - ply the vref voltage for ddr memory. an on-chip buffer amplifier outputs a low noise reference voltage equal to v ddqin /2. this output is capable of supplying 10ma . vttr has internal 0.01f capacitor. additional r-c filter can be used to further reduce the ripple on vttr. the error amplifier for channel 2 uses this voltage as its reference voltage. v ddqin (a4): external reference input for channel 2. an internal resistor divider sets the vttr pin voltage to be equal to half the voltage applied to this input. channel 2 uses the vttr pin voltage as its error amplifier reference. lt m4632 4632fc
8 for more information www.linear.com/ltm4632 block diagram decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 3.6v to 15v, v out = 1.5v) i out = 3a 4.7 10 f c out external output capacitor requirement (v in = 3.6v to 15v, v out = 1.5v) i out = 3a 10 22 f power control vttr 2.2f 0.01f 0.22f 10f intv cc vddqin vddq 0.1f track/ss1 run1 run2 sync/mode comp1 1f v out1 v in 10k pgood1 vddq 1.3v 3a v in 3.6v to 15v intv cc gnd 0.82h 4632 bd freq sgnd 312k internal comp comp2 fb1 60.4k 51.7k v out1 v out2 10k pgood2 intv cc 22f 0.22f 1f v out2 vtt 0.65v 3a gnd 0.82h 22f internal comp buffer lt m4632 4632fc
9 for more information www.linear.com/ltm4632 operation the ltm4632 is a dual output standalone non-isolated switch mode dc/dc power supply for ddr-qdr4 sram memory supplies and bus termination. it can deliver two output rails which could both sink and source 3a dc cur - rent with few external input and output ceramic capaci - tors, plus a 10ma buffered vttr (vref) reference voltage which equal to one half of v ddqin voltage. two or more module outputs can be easily paralleled to achieve a single vtt output with a higher sink and source current capability. up to 8 phases can be paralleled to run simultaneously with a good current sharing guaranteed by current mode control loop. this module provides precisely regulated output voltage (v out1 ) programmable via one external resistor from 0.6v to 2.5v over 3.6v to 15v input voltage range. with intv cc tied to v in , this module is able to operate from 3.3v input. the ltm4632 has an integrated a dual constant on-time valley current mode regulator, power mosfets, induc - tor, and other supporting discrete components. the typi - cal switching frequency is internally set to 1mhz . for switching noise-sensitive applications, the module can be externally synchronized to a clock within 30% of the set frequency. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4632 module has sufficient sta - bility margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast cur- rent limiting. an internal overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 8% window around the regulation point. furthermore, an input overvoltage protection been utilized by shutting down both power mosfets when v in rises above 17.5v to protect internal devices. pulling the run pin below 1v forces the controller into its shutdown state, turning off both power mosfets and most of the internal control circuitry. at light load cur - rents, burst mode operation can be enabled to achieve higher efficiency compared to continuous mode (ccm) by setting mode pin to intv cc . the track/ss pin is used for power supply tracking and soft-start programming. see the applications information section. applications information the typical ltm4632 application circuit is shown in figure 19. external component selection is primarily deter - mined by the input voltage, the output voltage and the maximum load current. refer to table 5 for specific exter - nal capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step down ratio that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits of the regulator. the minimum off-time limit imposes a maximum duty cycle which can be calculated as: d max = 1 C t off(min) ? f sw where t off(min) is the minimum off-time, 45ns typical for ltm4632, and f sw is the switching frequency. conversely the minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated as d min = t on(min) ? f sw where t on(min) is the minimum on-time, 20ns typical for ltm4632 . in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. note that additional thermal derating may be applied. see the thermal considerations and output current derating section in this data sheet. lt m4632 4632fc
10 for more information www.linear.com/ltm4632 applications information channel 1 output voltage programming (configured as vddq) the pwm controller for the v out1 has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor connects v out1 and fb1 pins together. adding a resistor r fb from fb1 pin to gnd pro - grams the output voltage: r f b = 0.6 v v o u t ? 0.6 v 60.4 k table 1. v fb resistor table (1%) vs various output voltages v out (v) 0.6 1.0 1.2 1.3 1.5 1.8 2.5 r fb (k) open 90.9 60.4 52.3 40.2 30.1 19.1 channel 2 output voltage programming (configured as vtt) the pwm controller for the v out2 uses vttr voltage as a reference voltage. v out2 is directly connected to the negative side of the error compiler to internally program v out2 to equal to vttr voltage, which equals to one half of v ddqin voltage. v out2 = vttr = v ddqin /2 in a complete ddr memory power application which require both vddq supply and vtt terminal outputs, configure ltm4632 channel 1 as vddq output by add - ing a feed-back resistor from fb1 pin to gnd. feed v out1 (vddq output) voltage to v ddqin pin to program channel 2 as vtt output which equals half of the channel 1 (vddq output) voltage. input decoupling capacitors the ltm4632 module should be connected to a low ac-impedance dc source. for each regulator channel, one piece 4.7f input ceramic capacitor is required for rms ripple current decoupling. bulk input capacitor is only needed when the input source impedance is com - promised by long inductive leads, traces or not enough source capacitance. the bulk capacitor can be an electro - lytic aluminum capacitor and polymer capacitor. without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i c i n ( r m s ) = i o u t ( m a x ) % ? d ? ( 1 C d ) where % is the estimated efficiency of the power module. output decoupling capacitors with an optimized high frequency, high bandwidth design, only single piece of 22f low esr output ceramic capaci - tor is required for each ltm4632 output to achieve low output voltage ripple and very good transient response. additional output filtering may be required by the sys - tem designer, if further reduction of output ripples or dynamic transient spikes is required. table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 0.75a (25%) load step transient. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancella - tion, but the output capacitance will be more a function of stability and transient response. the linear technology ltpowercad design tool is available to download online for output ripple, stability and transient response analysis and calculating the output ripple reduction as the number of phases implemented increases by n times. burst mode operation in applications where high efficiency at intermediate current are more important than output voltage ripple, burst mode operation could be used on channel 1 by connecting sync/mode pin to intv cc to improve light load efficiency. in burst mode operation, a current rever - sal comparator (irev) detects the negative inductor cur - rent and shuts off the bottom power mosfet, resulting in discontinuous operation and increased efficiency. both power mosfets will remain off and the output capacitor will supply the load current until the comp voltage rises above the zero current level to initiate another cycle. lt m4632 4632fc
11 for more information www.linear.com/ltm4632 applications information force continuous current mode (ccm) operation in applications where fixed frequency operation is more critical than low current efficiency, and where the low - est output ripple is desired, forced continuous opera - tion should be used. forced continuous operation can be enabled by tying the sync/mode pin to gnd. in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start- up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4632s output voltage is in regulation. operating frequency the operating frequency of the ltm4632 is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. the default operating frequency is internally set to 1mhz. in most appli - cations, no additional frequency adjusting is required. frequency synchronization the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock. the external clock frequency range must be within 30% around the set operating frequency. a pulse detection circuit is used to detect a clock on the sync/mode pin to turn on the phase locked loop. the pulse width of the clock has to be at least 100ns. the clock high level must be above 2v and clock low level below 0.3v . the presence of an external clock will place both regulator channels into forced continuous mode operation. during the start-up of the regulator, the phase-locked loop function is disabled. multiphase operation (configured as multiphase single output vtt) for vtt termination output loads that demand more than 3a of current, two outputs in the ltm4632 or even mul - tiple ltm4632s can be paralleled to run out of phase to provide a multiphase single output vtt termination supply capable of souring and sinking higher current. 33.2k 3.3 intv cc v + ph mod v out1 v out2 out1 0 0 90 270 4632 f02 180 v tt 12a 90 out2 set sync/ mode v out1 v out2 sync/ mode div gnd ltc6902 ltm4632 ltm4632 figure 2. example of clock phasing for 4-phase single output vtt operation with ltc6902 the two switching mode regulator channels inside the ltm4632 are internally set to operate 180 out of phase. multiple ltm4632 s could easily operate 90 degrees, 60 degrees or 45 degrees shift which corresponds to 4-phase, 6-phase or 8-phase operation by letting sync/ mode of the ltm4632 synchronize to an external multi - phase oscillator like ltc6902. figure 2 shows a 4-phase single output vtt termination supply design example for clock phasing. tie fb1 pin of the ltm4632 to its intv cc pin to put the module into two phase single vtt output operation mode. this will internally switch the channel 1 error amplifier reference voltage from 0.6v to vttr voltage, which is the same as channel 2. repeat this for each lt m4632 module in multiple ltm4632s paralleling application. also tie run, track/ss and comp pin of each paral - leling channel together. figure 20 shows an example of paralleled multiphase single output vtt termination sup - ply operation and pin connection. the ltm4632 device is an inherently current mode con - trolled device, so parallel modules will have very good cur - rent sharing. this will balance the thermals on the design. multiphase operation (configured as vddq+vtt) for application which both vddq and vtt termination output loads demand more than 3a of current, two or multiple channel 1 outputs from different ltm4632 mod - ules can be easily paralleled to provide a multiphase sin - gle vddq output while channel 2 outputs from different ltm4632 modules can paralleled to provide a multiphase single vtt output. lt m4632 4632fc
12 for more information www.linear.com/ltm4632 in this case, multiple ltm4632s should be setup to oper - ate 180 degrees, 120 degrees or 90 degrees shift which corresponds to 2-phase, 3-phase or 4- phase operation by letting sync/mode of the ltm4632 synchronize to an external multiphase oscillator like ltc6902. applications information 33.2k 3.3 intv cc v + ph mod v out1 v out2 out1 0 0 180 360 180 vddq 6a vtt 6a 180 out2 set sync/ mode v out1 v out2 sync/ mode div gnd 4632 f03 figure 3. example of clock phasing for 2-phase vddq plus 2- phase vtt operation with ltc6902 tie ru n1, track/ss1 fb1 and comp1 pin of each par - alleling module together for vddq output. tie ru n2, v ddqin , fb2 and comp2 pin of each paralleling module together for vtt output. figure 22 shows an example of two ltm4632 get paralleled to provide 6a vddq and 6a vtt termination supply. input and output rms ripple current cancellation a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input volt - age is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. duty cycle (v o ut / v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4632 f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase figure 4. input rms current ratios to dc load current as a function of duty cycle lt m4632 4632fc
13 for more information www.linear.com/ltm4632 applications information application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple cur - rent reduction as a function of the number of interleaved phases. figure 4 shows this graph. channel 1 output voltage tracking and soft-start the track/ss pin provides a means to either soft-start the channel 1 regulator or track it to a different power supply. a capacitor on the track/ss pin will program the ramp rate of the channel 1 output voltage. an internal 1.2a current source will charge up the external soft-start capacitor towards intv cc voltage. when the track/ss voltage is below 0.6v, it will take over the internal 0.6v reference voltage to control the output voltage. the total soft-start time can be calculated as: t s s = 0.6 ? c s s 1.2a where c ss is the capacitance on the track/ss pin. forced continuous mode are disabled during the soft- start process. channel 1 output voltage tracking can also be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. figure?5 and figure 6 show an example waveform and schematic of a ratiometric tracking where the slave regulator s output slew rate is proportional to the masters. since the slave regulator s track/ss is connected to the master s output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output voltage when track/ss voltage is below 0.6v, the slave output voltage and the master output voltage should sat - isfy the following equation during the start-up. v o u t ( s l ) r f b ( s l ) r f b ( s l ) + 60.4k = v o u t ( m a ) r t r ( b o t ) r t r ( t o p ) + r t r ( b o t ) the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure 6. following the upper equation, the masters output slew rate (mr) and the slave s output slew rate (sr) in volts/ time is determined by : m r s r = r f b ( s l ) r f b ( s l ) + 60.4k r t r ( b o t ) r t r ( t o p ) + r t r ( b o t ) for example, v out(ma) = 1.5v, mr = 1.5v/ 1ms and v out(sl) = 1.2v, sr = 1.2v/1ms. from the equation, we could solve out that r tr(top) = 60.4k and r tr(bot) = 40.2k is a good combination for the ratiometric tracking. time slave output master output output voltage 4632 f05 figure 5. output ratiometric tracking waveform the track pins will have the 1.2a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track pin offset to a negligible value. the coincident output tracking can be recognized as a special ratiometric output tracking which the master s output slew rate (mr) is the same as the slaves output slew rate (sr), as waveform shown in figure 7. lt m4632 4632fc
14 for more information www.linear.com/ltm4632 applications information from the equation, we could easily find out that, in the coincident tracking, the slave regulators track/ss pin resistor divider is always the same as its feedback divider. r f b ( s l ) r f b ( s l ) + 60.4k = r t r ( b o t ) r t r ( t o p ) + r t r ( b o t ) for example, r tr(top) = 60.4k and r tr(bot) = 60.4k is a good combination for coincident tracking for v out(ma) = 1.5v and v out(sl) = 1.2v application. v in v out1 v out2 vttr fb1 gnd ltm4632 comp1 comp2 intv cc v in 3.6v to 15v rail v out1 1.5v, 3a 10f 16v 0.1f 22f 4v run1 40.2k pgood1 pgood2 run2 sync/mode track/ss1 v ddqin v in v out1 v out2 vttr fb1 gnd ltm4632 comp1 comp2 intv cc v out2 1.2v, 3a 22f 4v run1 60.4k 4632 f06 40.2k 60.4k v out1 pgood1 pgood2 run2 sync/mode track/ss1 v ddqin figure 6. example schematic of ratiometric output voltage tracking time master output slave output output voltage 4632 f07 figure 7. output coincident tracking waveform lt m4632 4632fc
15 for more information www.linear.com/ltm4632 applications information power good the pgood pins are open drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 8% window around the regulation point. a resistor can be pulled up to a particular supply voltage for monitoring. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltm4632s pgood falling edge includes a blanking delay of approximately 40s. stability compensation the ltm4632 module internal compensation loop is de-signed and optimized for low esr ceramic output capacitors only application. table 5 is provided for most application requirements. the ltpowercad design tool is available to download for control loop analysis for further optimization. run enable pulling the run pin to ground forces the ltm4632 into its shutdown state, turning off both power mosfets and most of its internal control circuitry. tying the run pin voltage above 1.28v will turn on the entire chip. low input application the ltm4632 is capable to run from 3.3v input when the v in pin is tied to intv cc pin. see figure 21 for the application circuit. please note the intv cc pin has 3.6v abs max voltage rating. pre-biased output start-up (channel 1) there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the ltm4632 channel 1 can safely power up into a pre-biased output without discharging it. the ltm4632 accomplishes this by forcing discontinuous mode (dcm) operation until the track/ss1 pin voltage reaches 80% of the 0.6v reference voltage for channel 1. this will prevent the bg from turning on during the pre- biased output start-up which would discharge the out - put. do not pre-bias ltm4632 with a voltage higher than intv cc (3.3v) voltage. overtemperature protection the internal overtemperature protection monitors the junction temperature of the module. if the junction temperature reaches approximately 170 c , both power switches will be turned off until the temperature drops about 10c cooler. input overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the ltm4632 constantly monitors each v in pin for an overvoltage condition. when v in rises above 17.5v, the regulator suspends operation by shutting off both power mosfets on the correspond - ing channel. once v in drops below 16.5v, the regulator immediately resumes normal operation. the regulator executes its soft-start function when exiting an overvolt - age condition. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param- eters defined by jesd51-9 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per-formed on a module package mounted to a hardware test board also defined by jesd51-9 ( test boards for area array surface mount package thermal measurements ). the motivation for providing these thermal coefficients in found in jesd51-12 ( guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are in-and-of themselves not relevant to providing guidance of thermal performance ; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance per - taining to ones application-usage, and can be adapted to correlate thermal performance to one s own application. lt m4632 4632fc
16 for more information www.linear.com/ltm4632 the pin configuration section typically gives four thermal coefficients explicitly defined in jesd 51-12; these coef - ficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air ther - mal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operat - ing condition. 2. jcbottom , the thermal resistance from junction to ambient, is the natural convection junction-to-ambi - ent air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. applications information a graphical representation of the aforementioned ther - mal resistances is given in figure 8; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by je sd51 -12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module. for example, in nor - mal board-mounted applications, never does 100% of the device s total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module package as the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packageCgranted, in the absence of a heat sink and air - flow, a majority of the heat flow is into the board. within a sip (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing model - ing simplicityC but also, not ignoring practical realitiesC an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the module and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software-defined jedec environment consistent with jesd51-12 to predict power loss heat flow and tempera - ture readings at different interfaces that enable the cal - culation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the module with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simu - lated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-envi - ronment chamber while operating the device at the same lt m4632 4632fc
17 for more information www.linear.com/ltm4632 applications information power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves provided in other sections of this data sheet. after these laboratory test have been performed and correlated to the module model, then the jb and ba are summed together to correlate quite well with the module model with no airflow or heat sinking in a properly define cham - ber. this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because approximately 100% of power loss flows from the junc - tion through the board into ambient with no airflow or top mounted heat sink. the 1.0v, 1.5v, and 2.5v power loss curves in figures 9 to 11 can be used in coordination with the load current derat - ing curves in figures 12 to 17 for calculating an approxi - mate ja thermal resistance for the ltm4632 with no heat sinking and various airflow conditions. the power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 assuming junction temperature at 120 c . the derating curves are plotted with the output current starting at 6a by putting lt m4632 into two phase single output setup (figure 20) and the ambient temperature at 40c. these output voltages are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measure - ments in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating figure 8. graphical representation of jesd51-12 thermal coefficients curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient tempera - ture is increased. the monitored junction temperature of 120c minus the ambient operating temperature speci - fies how much module temperature rise can be allowed. as an example in figure 12 the load current is derated to ~3a at ~100c with no air or heat sink and the power loss for the 5v to 1v at 3a output is about 0.95w. the 0.95w loss is calculated with the ~0.7w room tempera - ture loss from the 5v to 1v power loss curve at 3a, and the 1.35 multiplying factor at 120c measured junction temperature. if the 100 c ambient temperature is sub - tracted from the 120 c junction temperature, then the difference of 20 c divided by 0.95w equals a 20 c /w ja thermal resistance. table 2 specifies a 19c~20c/w value which is very close. table 2 to 4 provide equivalent thermal resistances for 1.0v, 1.5v, and 2.5v outputs with and without airflow. the derived thermal resistances in table 2 to 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with the above ambient temperature multiplica - tive factors. the printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. 4638 f08 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance lt m4632 4632fc
18 for more information www.linear.com/ltm4632 applications information figure 12. 5v to 1.0v derating curve, no heat sink figure 13. 12v to 1.0v derating curve, no heat sink figure 14. 5v to 1.5v derating curve, no heat sink figure 15. 12v to 1.5v derating curve, no heat sink figure 16. 5v to 2.5v derating curve, no heat sink figure 17. 12v to 2.5v derating curve, no heat sink figure 9. 1.0v output power loss figure 10. 1.5v output power loss figure 11. 2.5v output power loss load current (a) 0 power loss (w) 4.0 3.6 2.8 3.2 2.4 1.6 2.0 1.2 0 0.4 0.8 2 1 4 4632 f09 6 3 5 12v in 5v in ambient temperature (c) 30 load current (a) 7 6 4 5 3 0 1 2 60 40 110 4632 f12 120 80 100 50 90 70 0lfm 200lfm 400lfm ambient temperature (c) 30 load current (a) 7 6 4 5 3 0 1 2 60 40 110 4632 f15 120 80 100 50 90 70 0lfm 200lfm 400lfm ambient temperature (c) 30 load current (a) 7 6 4 5 3 0 1 2 60 40 110 4632 f13 120 80 100 50 90 70 0lfm 200lfm 400lfm ambient temperature (c) 30 load current (a) 7 6 4 5 3 0 1 2 60 40 110 4632 f16 120 80 100 50 90 70 0lfm 200lfm 400lfm ambient temperature (c) 30 load current (a) 7 6 4 5 3 0 1 2 60 40 110 4632 f14 120 80 100 50 90 70 0lfm 200lfm 400lfm ambient temperature (c) 30 load current (a) 7 6 4 5 3 0 1 2 60 40 110 4632 f17 120 80 100 50 90 70 0lfm 200lfm 400lfm load current (a) 0 power loss (w) 4.0 3.6 2.8 3.2 2.4 1.6 2.0 1.2 0 0.4 0.8 2 1 4 4632 f10 6 3 5 12v in 5v in load current (a) 0 power loss (w) 4.0 3.6 2.8 3.2 2.4 1.6 2.0 1.2 0 0.4 0.8 2 1 4 4632 f11 6 3 5 12v in 5v in lt m4632 4632fc
19 for more information www.linear.com/ltm4632 applications information table 2. 1.0v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 12, 13 5, 12 figure 9 0 none 19 to 20 figures 12, 13 5, 12 figure 9 200 none 18 to 19 figures 12, 13 5, 12 figure 9 400 none 17 to 18 table 3. 1.5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 14, 15 5, 12 figure 10 0 none 19 to 20 figures 14, 15 5, 12 figure 10 200 none 18 to 19 figures 14, 15 5, 12 figure 10 400 none 17 to 18 table 4. 2.5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 16, 17 5, 12 figure 11 0 none 19 to 20 figures 16, 17 5, 12 figure 11 200 none 18 to 19 figures 16, 17 5, 12 figure 11 400 none 17 to 18 lt m4632 4632fc
20 for more information www.linear.com/ltm4632 v out (v) c in (ceramic) (f) c in (bulk) c out1 (ceramic) (f) c out2 (bulk) (f) c ff (pf) v in (v) droop (mv) p-p derivation (mv) recovery time (s) load step (a) load step slew rate (a/s) r fb (k) 1 2 10 0 1 47f 0 0 5, 12 0 77 15 0.75 10 90.9 1.2 2 10 0 1 47f 0 0 5, 12 0 83 15 0.75 10 60.4 1.5 2 10 0 1 47f 0 0 5, 12 0 94 18 0.75 10 40.2 1.8 2 10 0 1 47f 0 0 5, 12 0 105 20 0.75 10 30.1 2.5 2 10 0 1 47f 0 0 5, 12 0 138 20 0.75 10 19.1 applications information table 5. output voltage response for each regulator channel vs component matrix (refer to figure 19) 25% load step typical measured values c in (ceramic) part number value c out1 (ceramic) part number value c out2 (bulk) part number value murata grm188r61e475ke11# 4.7f, 25v, 0603, x5r murata grm21r60j476me15# 47f, 6.3v, 0805, x5r panasonic 6tpc150m 150f, 6.3v 3.5 2.8 1.4mm murata grm188r61e106ma73# 10f, 25v, 0603, x5r murata grm188r60j226m ea0# 22f, 6.3v, 0603, x5r taiyo yuden tmk212bj475kg-t 4.7f, 25v, 0805, x5r taiyo yuden jmk212bj476mg-t 47f, 6.3v, 0805, x5r lt m4632 4632fc
21 for more information www.linear.com/ltm4632 applications information safety considerations the ltm4632 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and over current protection. layout checklist/example the high integration of ltm4632 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid - erations are still necessary. ? use large pcb copper areas for high current paths, including v in , gnd, v out1 and v out2 . it helps to mini - mize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capac - itors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce mod - ule thermal stress, use multiple vias for interconnec - tion between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely con - nect these pins together. the track pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure 18 gives a good example of the recommended layout. gnd gnd c out c out c in c in v in v in figure 18. recommend pcb layout lt m4632 4632fc
22 for more information www.linear.com/ltm4632 applications information 52.3k 4632 f19 22f 25v v in 3.6v to 15v rail vddq 1.3v, 3a 22f 4v 22f 4v v out1 vtt 0.65v, 3a vttr 0.65v, 10ma v out2 fb1 vttr comp2 comp1 v ddqin vddq gnd ltm4632 pgood1 pgood2 v in run1 run2 intv cc sync/mode track/ss1 4632 f20 22f 25v v in 4v to 15v rail 47f 4v v out1 vtt 0.9v, 6a vttr 0.9v, 10ma 22f 25v 4 v out2 fb1 intv cc vttr comp2 comp1 v ddqin vddq gnd ltm4632 pgood1 pgood2 v in v out1 v out2 gnd ltm4630 v in run1 run2 intv cc sync/mode track/ss1 100f 4v 6 vddq 1.8v, 36a figure 19. 3.6v to 15v input, 1.3v/3a vddq, 0.65v/3a vtt and 10ma vttr design figure 20. 4v to 15v input, two phase single output 6a vtt termination design with ltm4630 36a vddq supply lt m4632 4632fc
23 for more information www.linear.com/ltm4632 applications information 40.2k 4632 f21 22f 6.3v v in 3.1v to 3.5v rail vddq 1.5v, 3a 22f 4v 22f 4v v out1 vtt 0.75v, 3a vttr 0.75v, 10ma v out2 fb1 vttr comp2 comp1 v ddqin vddq gnd ltm4632 pgood1 pgood2 v in run1 run2 intv cc sync/mode track/ss1 22f 25v v in 3.6v to 15v rail vddq 1.2v, 6a vtt 0.6v, 6a vttr 0.6v, 10ma 1f v out1 v out2 fb1 vttr comp1 comp2 v ddqin gnd ltm4632 pgood1 pgood2 v in run1 run2 intv cc intv cc intv cc sync/mode track/ss1 4632 f22 v out1 v out2 comp1 vttr fb1 v ddqin vddq gnd ltm4632 pgood1 pgood2 v in run1 run2 intv cc 30.2k 10 9 8 7 6 1 2 3 4 5 sync/mode track/ss1 comp2 set mod out3 gnd out4 ltc6902 33.2k v + div out2 ph out1 22f 4v 22f 4v figure 21. 3.3v input, 1.5v/3a vddq, 0.75v/3a vtt and 10ma vttr design figure 22. two module in parallel, 3.6v to 15v input, 1.2v/6a vddq, 0.6v/6a vtt and 10ma vttr design lt m4632 4632fc
24 for more information www.linear.com/ltm4632 ltm4632 component lga and bga pinout pin id function pin id function pin id function pin id function pin id function a1 v out2 a2 v in a3 vttr a4 v ddqin a5 comp2 b1 v out2 b2 run2 b3 v in b4 pgood2 b5 gnd c1 gnd c2 gnd c3 intv cc c4 sgnd c5 sync/mode d1 v out1 d2 run1 d3 v in d4 pgood1 d5 gnd e1 v out1 e2 v in e3 track/ss1 e4 fb1 e5 comp1 package row and column labeling may vary among module products. review each package layout carefully. package description lt m4632 4632fc
25 for more information www.linear.com/ltm4632 package description please refer to http: //www.linear.com/product/ltm4632#packaging for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 1 2 3 4 5 pin 1 ?b (25 places) d e e b f g detail a 0.3175 0.3175 lga 25 0613 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? lga package 25-lead (6.25mm 6.25mm 1.82mm) (reference ltc dwg # 05-08-1949 rev ?) 7 see notes notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. t he total number of pads: 25 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature 7 package row and column labeling may vary among module products. review each package layout carefully ! detail b detail b substrate mold cap // bbb z z a symbol a b d e e f g h1 h2 aaa bbb eee min 1.72 0.60 0.27 1.45 nom 1.82 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 max 1.92 0.66 0.37 1.55 0.15 0.10 0.15 notes dimensions total number of lga pads: 25 h2 h1 s y x z ? eee lt m4632 4632fc
26 for more information www.linear.com/ltm4632 package description please refer to http: //www.linear.com/product/ltm4632#packaging for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 0.630 0.025 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 1 2 3 4 5 pin 1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature ?b (25 places) a detail b package side view z m x y z ddd m z eee a2 d e e b f g detail a 0.3175 0.3175 bga 25 0515 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? bga package 25-lead (6.25mm 6.25mm 2.42mm) (reference ltc dwg # 05-08-1502 rev ?) detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.22 0.50 1.72 0.60 0.60 0.27 1.45 nom 2.42 0.60 1.82 0.75 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 max 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 25 // bbb z z h2 h1 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes lt m4632 4632fc
27 for more information www.linear.com/ltm4632 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 05/16 added bga package 1, 2, 26 b 09/16 corrected equations of tracking start-up time from r tr(top) /[r tr(top) + r tr(bot) ] to r tr(bot) /[r tr(top) + r tr(bot) ] 13, 14 c 05/17 changed vddq to 1.3v/3a and vtt to 0.65v 22 lt m4632 4632fc
28 for more information www.linear.com/ltm4632 ? linear technology corporation 2016 lt 0517 rev c ? printed in usa www.linear.com/ltm4632 related parts package photo design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technology s family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. part number description comments ltm4622 ultrathin, dual 2.5a or single 5a step-down module regulator 3.6v < v in < 20v, 0.6v < v out < 5.5v, 6.25mm 6.25mm 1.82mm lga package, 6.25mm 6.25mm 2.42 bga package ltm4623 ultrathin, single 3a step-down module regulator 4v v in 20v, 0.6v v out 5.5v, 6.25mm 6.25mm 1.82mm lga package, 6.25mm 6.25mm 2.42 bga package ltm4644 quad 4a step-down module regulator 4v < v in < 14v, 0.6v < v out < 5.5v, 9mm 15mm 5.01mm bga package ltm4630 module regulator for higher power vddq supply 4.5v < v in < 15v, 0.6v LTM4650 module regulator for high power fpga/asic core supply 4.5v < v in < 15v, 0.6v

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